Anti-FPGA/ASIC POW Mining ALGO for DERO.
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# Anti-FPGA/ASIC POW Mining ALGO

FPGA relies on doing more work per clock by using a custom circuit design. Plan to defeat about using loops and certain branches taking more time, leading to ineffective usage of resources and pipeline stalls.
NOTE : Above will not defeat FPGA as FPGA can do everything in a single cycle. In-fact we would need 32 different operators but we will use only following 12, Rest is defeated by using branch behavior of the large switch. The different instructions to defeat SIMD will be +, - , *, XOR, NOT, AND, Shift Left, Shift Right, Reverse Bits, popcnt(1s). ROTATE Right, Rotate Left, [Rotate left/rotate with rotate amount is considered different instruction] and expand to 6 instructions

``````step_3[i] += step_3[i] // +
step_3[i] -= (step_3[i] ^ 91)// XOR and -
step_3[i] *= step_3[i] // *
step_3[i] = step_3[i]^step_3[pos2] // XOR
step_3[i] =  ^step_3[i]  // binary NOT operator
step_3[i] = step_3[i] & step_3[pos2] // AND
step_3[i] = step_3[i] << (step_3[i]&3) // shift left
step_3[i] = step_3[i] >> (step_3[i]&3) // shift right
step_3[i] = bits.Reverse8(step_3[i]) // reverse bits
step_3[i] = step_3[i] ^ byte(bits.OnesCount8(step_3[i])) // ones count bits
step_3[i] = bits.RotateLeft8(step_3[i], int(step_3[i]) ) // rotate  bits by random
step_3[i] = bits.RotateLeft8(step_3[i], 1 ) // rotate  bits by 1
step_3[i] = step_3[i]^bits.RotateLeft8(step_3[i], 2 ) // rotate  bits by 2
step_3[i] = bits.RotateLeft8(step_3[i], 3 ) // rotate  bits by 3
step_3[i] = step_3[i]^bits.RotateLeft8(step_3[i], 4 ) // rotate  bits by 4
step_3[i] = bits.RotateLeft8(step_3[i], 5 ) // rotate  bits by 5
``````

Few high end FPGAs in market are: Virtex UltraScale+ VU19P having 35 billion transistors, 9 million logic cells.
The Stratix 10 GX 10M 10.2 million logic elements. So we plan to smartly place a million if then else with some random code sprinkled, It will be far above the emulation capacity this may mean constants, prime numbers etc. Some of the steps are nonlinear due to number of reasons such as buffer length is different between each run.

NOTE: Please provide any suggestions to improve the ALGO & increase FPGA resistance here.